Market demand for smaller, lighter, and more powerful electronic devices drives the development of more compact packages and increased functionality. Demand for electronic devices, such as cellular telephones, personal digital assistants, and portable computing devices, contributes heavily to the overall market demand. Development of more compact packages and increased functionality has led to packaging technologies such as fine pitch ball grid arrays (FBGA), chip scale packages (CSP), wafer level packaging (WLP), multi-chip module (MCM) technology, and stacked die packaging. An MCM includes multiple semiconductor die in one package, such as multiple stacked die in a CSP or multiple stacked die on a BGA. Increasing the functionality has led to system in package (SiP) solutions.
SiP products are fully functional systems or sub-systems in a semiconductor package. Typically, SiP products include components that are traditionally found on a system mother board. These components include integrated circuit chips or die, surface mount discrete passive components, integrated passive networks, passive components embedded or patterned into the package substrate, filters, electromagnetic interference shields, and micro-electromechanical system (MEMS) devices including semiconductor sensors and semiconductor lasers. Some SiP products use stacked die packaging technology.
In stacked die packaging, semiconductor dice are stacked in the third dimension as opposed to the two area dimensions. The semiconductor dice are stacked one semiconductor die on top of another semiconductor die and electrically interconnected in a single package. Stacking semiconductor dice in the third dimension increases efficient use of printed circuit board area. Using stacked die packaging results in smaller and lighter packages, reduced packaging costs, reduced system level costs for SiP products, and reduced system level sizes due to smaller footprints and decreased component count. Applications include flash memory and static random access memory (SRAM) combinations used in cellular systems.
Different technologies have been explored for stacking and connecting semiconductor dice in a stacked die package. Typically, stacked die are arranged in a pyramid stacked die configuration or an overhanging stacked die configuration. Wire bonding is a popular interconnection method due to existing infrastructure, flexibility, and cost advantages. In a pyramid stacked die configuration, a smaller die is placed on top of a larger die and a wire loop from the top die clears the edge of the bottom die as well as the wire loops of the bottom die. In an overhanging stacked die configuration, a larger die is placed on top of a smaller die and a spacer situated between the semiconductor dice provides space for the wire loops of the bottom die. In each configuration, spacers may be situated between the semiconductor dice, which increases production time, inventories, and system costs.
For these and other reasons there is a need for the present invention.